  Temporal logic in finite-state verification. From Wikipedia, the free encyclopedia ... Finite-state machines. Formal methods. Formal verification. Kripke ...
http://en.wikipedia.org/wiki/Temporal_logic_in_finite-state_verification |
Scientific documents that cite the following paper: Automatic verification of finite-state concurrent systems using temporal logic specifications, by E. M. Clarke, ...
http://citeseerx.ist.psu.edu/showciting?doi=10.1.1.92.9102 |
... expressed in a (propositional, branching-time) temporal logic. ... verification of finite-state concurrent systems using temporal logic ...
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.92.9102 |
... verification of finite-state concurrent systems using temporal logic specifications ... explosion problem in temporal logic model checking, Proceedings ...
http://portal.acm.org/citation.cfm?coll=GUIDE&dl=GUIDE&id=5399 |
Temporal logic has found an important application in formal verification, where ... Temporal logic in finite-state verification. Temporal logic of actions (TLA) ...
http://en.wikipedia.org/wiki/Temporal_logic |
Temporal logic has found an important application in formal verification, where ... Temporal logic in finite-state verification. Temporal Logic of Actions (TLA) ...
http://kiwitobes.com/wiki/Temporal_logic.html |
... 1981. Design and verification of synchronization skeletons using branching time temporal logic. In Logics of Programs ... finite state program M meets a ...
http://citeseer.ist.psu.edu/context/270439/0 |
Document details from CiteSeerX (Isaac Councill, Lee Giles): ABSTRACT: Temporal logic model checking is an automatic technique for verifying finite-state concurrent ...
http://serv2.ist.psu.edu:8080/viewdoc/summary?doi=10.1.1.30.1789 |
E. M. Clarke, E. A. Emerson, and A. P. Sistla. Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications. ACM Transactions on ...
http://citeseer.ist.psu.edu/cs?q=dbnum%3D1%2CGID%3D9597%2CDID%3D0%2Cstart%3D50%2Ccluster%3Dnone%2Cqtype%3Dcontext: |
Verification of digital circuits in higher order logic often requires the proof of temporal propositional logic formulae. The implementation of decision procedures ...
http://citeseer.comp.nus.edu.sg/3935.html |
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